As part of this initiative, Analogue Insight and Tetrivis have signed a Memorandum of Understanding (MoU) to jointly develop the chiplet, aligning their IP roadmaps, technology resources, and customer ...

Codasip, the European RISC-V leader, has made available an exploration platform based on the Codasip X730 application core, which integrates CHERI (Capability Hardware Enhanced RISC Instructions).

Trusted Semiconductor Design Partner Combines Deep Expertise with a Fresh Vision to Deliver High-Performance Custom Chip Solutions for AI, Automotive, 5G, networking, and other applications READING, U ...

The ENS92051 is the dual-beam Ku-band receiver (Rx) supporting eight channels with separate amplitude and phase control. The Rx carrier frequency range is 10.7 to 12.75 GHz with an instantaneous ...

Expedera launches its Origin Evolution NPU IP, bringing hardware acceleration to meet the computational demands of running ...

SINGAPORE -- May, 20 2025 – GlobalFoundries (Nasdaq: GFS) (GF) today announced plans to expand its capabilities in advanced packaging through a new Memorandum of Understanding (MOU) signed with the ...

"Native Red Hat Enterprise Linux support on SiFive’s HiFive Premier P550 board offers developers a substantial enterprise-grade toolchain for RISC-V. This is a pivotal step forward in enabling a ...

In fifteen years, RISC-V has gone from an academic project at UC Berkeley to one of the major technological trends in compute. The ISA has since flourished in an era that appreciates its royalty-free, ...

Intel's cost-cutting measures look set to continue as it's reportedly looking to divest its network and edge businesses. Reuters reports that the embattled firm is looking to sideline parts of the ...

The Samsung SAFE™ program is designed to foster close collaboration between Samsung Foundry and its partners, encouraging innovation and efficiency across the semiconductor design ecosystem. By ...

Attendees of the Summit can visit BrainChip at booth #716 to see live demonstrations of the company’s latest advancements in Edge AI technology, including innovations in on-chip language processing, ...

Creonic GmbH, a leading provider of ready-to-use IP cores for ASIC and FPGA applications, announces the release of its new oFEC (Open Forward Error Correction) codec IP core. The solution supports ...